Relay release delay circuit

ABSTRACT

A circuit is disclosed that is connected to the driving conductor of a relay to increase the relay&#39;&#39;s release time. The circuit includes an RC timing circuit that is effective to maintain an amplifier circuit in a non-conductive state. The application of an operating potential to the driving conductor discharges the capacitor which switches the amplifier to the conductive state to maintain the relay operated for a period of time determined by the RC constants of the circuit. The circuit has a variable level limit for the capacitor charge to maintain the time interval constant in spite of voltage source variations.

[21] Appl. No.: 139,336

Blauert ..3l7/14l S United States Patent 1 [111 3,732,467 Mills 1 May 8, 1973 [54] RELAY RELEASE'DELAY CIRCUIT 3,165,648 1/1965 Sainsbury ..307/293 3,287,608 1 1/l966 Pokrant ..307/293 X Inventor: J y Mllls, Forest Park, 3,376,429. 4/1968 Atkins et al. ..3o1/293x Assigneez Autamatic Electric Labora- Armstrong X tories Incorporated, North Lake, 111. Primary ExaminerStanley D. Miller, Jr. Filed: y 1971 Attorney-K. Mullerheim, B. E. Franz and Theodore C. Jay, Jr.

[ ABSTRACT I A circuit is disclosed that is connected to the driving conductor of a relay to increase the relays release 1 Claim, 1 Drawing Figure Clku- PATENTED HAY 81973 NKU INVENTOR JEFFREY P. MILLS BY h 5.7% ATTORNEY BACKGROUND OF THE INVENTION 1. Field of the Invention This invention pertains to circuits for maintaining a relay in the operated state for a fixed period of time after the operating drive is removed and more particularly to decrease the potential variations of this delay period.

2. Description of the Prior Art In electromechanical telephone systems the most frequently used relay is the telephone type relay as disclosed in US. Pat. No. 2,401,213. This type of relay may be made to release slowly by including a large copper sleeve on the heel end of its coil. Many telephone switching system control operations require the slow release characteristic, and this method is the classical one that has been used.

In the currently available electronic telephone systems the number of applications where a slow releasing relay is needed is considerably reduced, since many of the relay functions are taken over by electronic logic. However, to eliminate all such applications would be impractical, and it is still necessary in certain operations to provide the capability of a slow release relay.

Electronic switching systems use correed relays of the type disclosed in US. Pat. No. 3,188,424. Due to the mechanical structure of correeds they cannot be made to release slowly by means of the copper slug used for this purpose on conventional telephone type relays. Therefore a different approach is necessary.

It is possible to delay the release of any relay by connecting a large capacitor in parallel with its coil, and this method has been used to a limited extent. Its chief disadvantages are: that the capacitor must be very large and that the delay time may vary over a large range, up to 300 percent. For many applications so large a variation is unacceptable. The variation in the delay time is due to: the wide tolerance associated with a large capacitor, the dependence of the delay time on coil resistance and temperature, and its dependence on the stability of the supply voltage.

SUMMARY OF THE INVENTION Accordingly, it is an object of this invention to reduce the variations in the timing of the release interval. This is accomplished in the circuit of the present invention by the combination of three expedients. The size of the capacitor is reduced to reasonable size and tolerance by the use of a transistor amplifier. The use of a transistor amplifier also makes the time delay independent of coil resistance and temperature. And most importantly, a reference voltage is established which varies in proportion to the battery supply voltage. This latter feature insures the constancy of the time delay interval as the battery voltage varies in its nominal range of 44 to 56 volts.

BRIEF DESCRIPTION OF THE DRAWING The single FIGURE is a schematic diagram of a circuit embodying the principles of this invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT In the figure the relay RLY is that whose release time is to be delayed. It is shown as having one terminal of its winding connected to a source of negative potential 1 l and the other terminal of its winding connected via a diode CR2 to one terminal of a switch SW. The other terminal of the switch is connected to a source of positive potential 10. Operation of the switch to its closed position completes the operate circuit for the relay causing it to operate. The switch SW is merely symbolic, it may be a switch as shown, but more likely it would be a semiconductor switch when used in an electronic switching system. Without the remainder of the circuit, operation of the switch to its open circuit state would cause the relay to fall back or release almost instantaneously. The circuit shown connected between the switch terminal and the relay terminal, in its normal state with the switch unoperated has the transistors Q1 and Q2 cut off. Grounding the input from the switch causes a current to flow from grounded terminal 10 through switch SW diode CR1 and resistor R10 to discharge capacitor C1. The shifting of this voltage level at the ungrounded plate of capacitor C1 turns on transistor Q1 via its connection through resistor R8 to the base of Q1. Current now flows from ground potential through resistors R2 and R3, the collector to emitter path of transistor Q1 through the emitter to collector path of transistor Q3 and resistor R5 to negative battery. Transistor Q2 is turned on by the collector current of transistor Q1 through resistor R3, one terminal of which is connected to the base of transistor Q2. The current flow is from ground potential through diode CR3, the emitter to collector path of transistor Q2, through the coil of relay RLY to negative battery at terminal 11. Resistor R1 serves to draw a current through diode CR3 to maintain the emitter of Q2 at a constant bias voltage level above ground potential. Diode CR4 is for the purpose of shunting the current induced by the collapsing field of the relay.

With only the circuit as described to this point, the operation would be such as to provide a release delay for the relay RLY, but it would be dependent upon the source voltage level. The charge path for capacitor C1 is from the negative potential source through resistor R9 and also through resistor R8 and transistor Q1. With a higher source voltage, the capacitor C1 would charge up faster thus decreasing the delay interval. While with a lower source voltage the rate of charge would be slower and the overall interval would be increased.

To overcome this, a reference voltage that varies proportionally with the source is provided for the capacitor C1 via diode CR5. This reference voltage is derived by the voltage divider consisting of resistors R6 and R7. Transistor Q3 with its base connected to this voltage divider and its emitter connected to ground via resistor R4, is an emitter follower which amplifies the current output of the voltage divider and provides a low impedance source of the reference voltage.

Removing the ground from the input causes capacitor C1 to begin charging due to the current through resistors R8 and R9. The time required for capacitor C1 to charge to the reference voltage will be approximately equal to the capacity of C1 times the parallel combination of resistors R8 and R9, the time constant of this resistor capacitor network. While capacitor C1 is charging, transistors Q1 and Q2 are conducting, but when capacitor C1 becomes charged to this reference voltage, both transistors Q1 and Q2 will be turned off and the relay will be released.

The rate of charge of capacitor C1 is necessarily proportional to the source voltage. Since the reference voltage is also proportional to the source voltage, these two factors will nullify each other when the delay time is computed. Therefore, the delay time is completely independent of the source voltage. The actual delay time is only dependent on the values chosen for resistors R8 and R9 and capacitor C1, their respective tolerances, and the junction parameters of transistor Q1.

What is claimed is:

1. In combination with a relay: a source of energizing potential having a first polarity terminal and a second polarity terminal, said source being subject to voltage variations; a terminal of said relay operate winding connected to said first polarity terminal, operating means for operating said relay and connect means joining said operating means to another terminal of said relay, said operating means effective upon operation to apply a potential of said second polarity terminal to operate said relay, a relay release delay means having an input connected to said operating means and an output connected to said other terminal of said relay and comprising a first voltage divider, a first amplifier normally in a non-conductive state, said amplifier including first and second transistors each having a plurality of electrodes including an emitter, a collector and a base electrode, means for providing operating potentials to said electrodes for maintaining them in a normally non-conductive state, means for connecting said first transistor base to said operating means via said first voltage divider, said first and second transistors placed in a conductive state upon operation of said operate means, means connecting said second transistor base to said first transistor collector and other means connecting said second transistor collector to said relay other terminal whereby said relay is maintained in an operated condition during the conductive state of said transistors, a capacitor having a first plate connected to said second polarity terminal, and a second plate connected to an intermediate point of said voltage divider, a capacitor charging resistor connected from said first polarity voltage terminal to said first voltage divider intermediate point to maintain said capacitor in a charged state, a second voltage divider connected between said first polarity terminal and said second polarity terminal, a third transistor means providing operating potentials to said emitter and collector electrodes of said third transistor, said third transistor base electrode connected to the intermediate point of said second voltage divider and means including a blocking diode connecting said third transistor emitter through said blocking diode to said capacitor second plate to thereby maintain said capacitor at a charge level related to the voltage level of said energizing potential source. 1 

1. In combination with a relay: a source of energizing potential having a first polarity terminal and a second polarity terminal, said source being subject to voltage variations; a terminal of said relay operate winding connected to said first polarity terminal, operating means for operating said relay and connect means joining said operating means to another terminal of said relay, said operating means effective upon operation to apply a potential of said second polarity terminal to operate said relay, a relay release delay means having an input connected to said operating means and an output connected to said other terminal of said relay and comprising a first voltage divider, a first amplifier normally in a non-conductive state, said amplifier including first and second transistors each having a plurality of electrodes including an emitter, a collector and a base electrode, means for providing operating potentials to said electrodes for maintaining them in a normally non-conductive state, means for connecting said first transistor base to said operating means via said first voltage divider, said first and second transistors placed in a conductive state upon operation of said operate means, means connecting said second transistor base to said first transistor collector and other means connecting said second transistor collector to said relay other terminal whereby said relay is maintained in an operated condition during the conductive state of said transistors, a capacitor having a first plate connected to said second polarity terminal, and a second plate connected to an intermediate point of said voltage divider, a capacitor charging resistor connected from said first polarity voltage terminal to said first voltage divider intermediate point to maintain said capacitor in a charged state, a second voltage divider connected between said first polarity terminal and said second polarity terminal, a third transistor means providing operating potentials to said emitter and collector electrodes of said third transistor, said third transistor base electrode connected to the intermediate point of said second voltage divider and means including a blocking diode connecting said third transistor emitter through said blocking diode to said capacitor second plate to thereby maintain said capacitor at a charge level related to the voltage level of said energizing potential source. 